An important objective in the advancement of integrated circuit (IC) technology is the reduction of IC dimensions. Such reduction of IC dimensions reduces area capacitance and is critical to increasing the performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are among the driving forces to constantly scale down IC dimensions.
As the density of semiconductor devices increases, however, the resistance capacitance (RC) delay time increasingly dominates the circuit performance. To reduce the RC delay, there is a desire to switch from conventional dielectrics to low-k dielectrics, which have a dielectric constant less than silicon dioxide (SiO2), or about 4.0. Low-k dielectrics may also include a class of low-k dielectrics frequently called extreme low-k (ELK) dielectrics, which have a dielectric constant less than about 2.5 or even about 2.0. Low-k materials are particularly useful as intermetal dielectrics (IMDs) and as interlayer dielectrics (ILDs). Despite their advantages, low-k materials raise many problems relating to their integration into conventional processing methods.
For example, many processing methods are used to pattern low-k materials (e.g., etching, chemical mechanical polish (CMP), and the like) for the formation of conductive interconnect structures or other structures in an IC device. These processes may cause surface damage to low-k materials because low-k materials tend to be softer, less chemically stable, more porous, or any combination of these factors. The damaged surface manifests itself in higher leakage currents, lower breakdown voltages, undesirable hydrophilic traits, and changes in the dielectric constant associated with the low-k dielectric material. Some damaged low-k dielectric surfaces may also lead to further processing problems (e.g., deformation during exposure to wet chemical cleanups, pattern misalignment, and the like) in subsequent processing steps.